xiic_l.h

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/******************************************************************************
 * Copyright (C) 2002 - 2021 Xilinx, Inc.  All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
/****************************************************************************/
#ifndef XIIC_L_H /* prevent circular inclusions */
#define XIIC_L_H /* by using protection macros */
 
#ifdef __cplusplus
extern "C" {
#endif
 
/***************************** Include Files ********************************/
 
#include "xil_io.h"
#include "xil_types.h"
 
/************************** Constant Definitions ****************************/
 
#define XIIC_DGIER_OFFSET 0x1C    
#define XIIC_IISR_OFFSET 0x20     
#define XIIC_IIER_OFFSET 0x28     
#define XIIC_RESETR_OFFSET 0x40   
#define XIIC_CR_REG_OFFSET 0x100  
#define XIIC_SR_REG_OFFSET 0x104  
#define XIIC_DTR_REG_OFFSET 0x108 
#define XIIC_DRR_REG_OFFSET 0x10C 
#define XIIC_ADR_REG_OFFSET 0x110 
#define XIIC_TFO_REG_OFFSET 0x114 
#define XIIC_RFO_REG_OFFSET 0x118 
#define XIIC_TBA_REG_OFFSET 0x11C 
#define XIIC_RFD_REG_OFFSET 0x120 
#define XIIC_GPO_REG_OFFSET 0x124 
/* @} */
 
#define XIIC_GINTR_ENABLE_MASK 0x80000000 
/* @} */
 
#define XIIC_INTR_ARB_LOST_MASK 0x00000001 
#define XIIC_INTR_TX_ERROR_MASK 0x00000002 
#define XIIC_INTR_TX_EMPTY_MASK 0x00000004 
#define XIIC_INTR_RX_FULL_MASK 0x00000008  
#define XIIC_INTR_BNB_MASK 0x00000010      
#define XIIC_INTR_AAS_MASK 0x00000020      
#define XIIC_INTR_NAAS_MASK 0x00000040     
#define XIIC_INTR_TX_HALF_MASK 0x00000080  
#define XIIC_TX_INTERRUPTS                                                     \
  (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
 
#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
 
/* @} */
 
#define XIIC_RESET_MASK 0x0000000A 
/* @} */
 
#define XIIC_CR_ENABLE_DEVICE_MASK 0x00000001  
#define XIIC_CR_TX_FIFO_RESET_MASK 0x00000002  
#define XIIC_CR_MSMS_MASK 0x00000004           
#define XIIC_CR_DIR_IS_TX_MASK 0x00000008      
#define XIIC_CR_NO_ACK_MASK 0x00000010         
#define XIIC_CR_REPEATED_START_MASK 0x00000020 
#define XIIC_CR_GENERAL_CALL_MASK 0x00000040   
/* @} */
 
#define XIIC_SR_GEN_CALL_MASK                                                  \
  0x00000001 
#define XIIC_SR_ADDR_AS_SLAVE_MASK                                             \
  0x00000002                             
#define XIIC_SR_BUS_BUSY_MASK 0x00000004 
#define XIIC_SR_MSTR_RDING_SLAVE_MASK                                          \
  0x00000008                                  
#define XIIC_SR_TX_FIFO_FULL_MASK 0x00000010  
#define XIIC_SR_RX_FIFO_FULL_MASK 0x00000020  
#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x00000040 
#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x00000080 
/* @} */
 
#define XIIC_TX_DYN_START_MASK 0x00000100 
#define XIIC_TX_DYN_STOP_MASK 0x00000200  
#define IIC_TX_FIFO_DEPTH 16              
/* @} */
 
#define IIC_RX_FIFO_DEPTH 16 
/* @} */
 
#define XIIC_TX_ADDR_SENT 0x00
#define XIIC_TX_ADDR_MSTR_RECV_MASK 0x02
 
#define XIIC_READ_OPERATION 1  
#define XIIC_WRITE_OPERATION 0 
#define XIIC_MASTER_ROLE 1 
#define XIIC_SLAVE_ROLE 0  
#define XIIC_STOP                                                              \
  0x00 
#define XIIC_REPEATED_START                                                    \
  0x01 
/***************** Macros (Inline Functions) Definitions *********************/
 
#define XIic_In32 Xil_In32
#define XIic_Out32 Xil_Out32
 
/****************************************************************************/
#define XIic_ReadReg(BaseAddress, RegOffset)                                   \
  XIic_In32((BaseAddress) + (RegOffset))
 
/***************************************************************************/
#define XIic_WriteReg(BaseAddress, RegOffset, RegisterValue)                   \
  XIic_Out32((BaseAddress) + (RegOffset), (RegisterValue))
 
/******************************************************************************/
#define XIic_IntrGlobalDisable(BaseAddress)                                    \
  XIic_WriteReg((BaseAddress), XIIC_DGIER_OFFSET, 0)
 
/******************************************************************************/
#define XIic_IntrGlobalEnable(BaseAddress)                                     \
  XIic_WriteReg((BaseAddress), XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK)
 
/******************************************************************************/
#define XIic_IsIntrGlobalEnabled(BaseAddress)                                  \
  (XIic_ReadReg((BaseAddress), XIIC_DGIER_OFFSET) == XIIC_GINTR_ENABLE_MASK)
 
/******************************************************************************/
#define XIic_WriteIisr(BaseAddress, Status)                                    \
  XIic_WriteReg((BaseAddress), XIIC_IISR_OFFSET, (Status))
 
/******************************************************************************/
#define XIic_ReadIisr(BaseAddress) XIic_ReadReg((BaseAddress), XIIC_IISR_OFFSET)
 
/******************************************************************************/
#define XIic_WriteIier(BaseAddress, Enable)                                    \
  XIic_WriteReg((BaseAddress), XIIC_IIER_OFFSET, (Enable))
 
/******************************************************************************/
#define XIic_ReadIier(BaseAddress) XIic_ReadReg((BaseAddress), XIIC_IIER_OFFSET)
 
/******************************************************************************/
#define XIic_ClearIisr(BaseAddress, InterruptMask)                             \
  XIic_WriteIisr((BaseAddress), XIic_ReadIisr(BaseAddress) & (InterruptMask))
 
/******************************************************************************/
#define XIic_Send7BitAddress(BaseAddress, SlaveAddress, Operation)             \
  {                                                                            \
    u8 LocalAddr = (u8)(SlaveAddress << 1);                                    \
    LocalAddr = (LocalAddr & 0xFE) | (Operation);                              \
    XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET, LocalAddr);                \
  }
 
/******************************************************************************/
#define XIic_DynSend7BitAddress(BaseAddress, SlaveAddress, Operation)          \
  {                                                                            \
    u8 LocalAddr = (u8)(SlaveAddress << 1);                                    \
    LocalAddr = (LocalAddr & 0xFE) | (Operation);                              \
    XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET,                            \
                  XIIC_TX_DYN_START_MASK | LocalAddr);                         \
  }
 
/******************************************************************************/
#define XIic_DynSendStartStopAddress(BaseAddress, SlaveAddress, Operation)     \
  {                                                                            \
    u8 LocalAddr = (u8)(SlaveAddress << 1);                                    \
    LocalAddr = (LocalAddr & 0xFE) | (Operation);                              \
    XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET,                            \
                  XIIC_TX_DYN_START_MASK | XIIC_TX_DYN_STOP_MASK | LocalAddr); \
  }
 
/******************************************************************************/
#define XIic_DynSendStop(BaseAddress, ByteCount)                               \
  {                                                                            \
    XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET,                            \
                  XIIC_TX_DYN_STOP_MASK | ByteCount);                          \
  }
 
/************************** Function Prototypes *****************************/
 
unsigned XIic_Recv(UINTPTR BaseAddress, u8 Address, u8 *BufferPtr,
                   unsigned ByteCount, u8 Option);
 
unsigned XIic_Send(UINTPTR BaseAddress, u8 Address, u8 *BufferPtr,
                   unsigned ByteCount, u8 Option);
 
unsigned XIic_DynRecv(UINTPTR BaseAddress, u8 Address, u8 *BufferPtr,
                      u8 ByteCount);
 
unsigned XIic_DynSend(UINTPTR BaseAddress, u16 Address, u8 *BufferPtr,
                      u8 ByteCount, u8 Option);
 
int XIic_DynInit(UINTPTR BaseAddress);
 
u32 XIic_CheckIsBusBusy(UINTPTR BaseAddress);
 
u32 XIic_WaitBusFree(UINTPTR BaseAddress);
 
#ifdef __cplusplus
}
#endif
 
#endif /* end of protection macro */