libpynq (release 5EWC0-2023 version 0.2.4 of 2023-10-07 15:07)
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iic.c
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1/*
2Copyright (c) 2023 Eindhoven University of Technology
3
4Permission is hereby granted, free of charge, to any person obtaining a copy
5of this software and associated documentation files (the "Software"), to deal
6in the Software without restriction, including without limitation the rights
7to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8copies of the Software, and to permit persons to whom the Software is
9furnished to do so, subject to the following conditions:
10
11The above copyright notice and this permission notice shall be included in all
12copies or substantial portions of the Software.
13
14THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20SOFTWARE.
21*/
22#include "iic.h"
24#include "log.h"
25#include <platform.h>
26#include <stdio.h>
27#include <string.h>
28#include <time.h>
29#include <xiic_l.h>
30
31#include <unistd.h>
32
33#define IIC_TIMEOUT 5
34typedef enum {
38 IIC_WRITE = 3
39
41
42typedef struct IICHandle {
44 volatile uint32_t *ptr;
45
46 // Register interface for slave mode.
47 uint32_t *register_map;
49
50 uint8_t saddr;
52 uint32_t new_val;
53 uint32_t recv_cnt;
57
58static IICHandle iic_handles[NUM_IICS] = {
59 {.ptr = NULL,
60
61 .saddr = 0,
62 .register_map = NULL,
63 .register_map_length = 0,
64 .selected_register = 0,
65 .state = IIC_IDLE,
66 .addressed = 0},
67};
68
69#define IIC_STOP 0x00
70#define IIC_REPEATED_START 0x01
71
72#define IIC_DGIER_OFFSET 0x1C
73#define IIC_IISR_OFFSET 0x20
74#define IIC_IIER_OFFSET 0x28
75#define IIC_RESETR_OFFSET 0x40
76#define IIC_CR_REG_OFFSET 0x100
77#define IIC_SR_REG_OFFSET 0x104
78#define IIC_DTR_REG_OFFSET 0x108
79#define IIC_DRR_REG_OFFSET 0x10C
80#define IIC_ADR_REG_OFFSET 0x110
81#define IIC_TFO_REG_OFFSET 0x114
82#define IIC_RFO_REG_OFFSET 0x118
83#define IIC_TBA_REG_OFFSET 0x11C
84#define IIC_RFD_REG_OFFSET 0x120
85#define IIC_GPO_REG_OFFSET 0x124
87#define IIC_CR_ENABLE_DEVICE_MASK 0x00000001
88#define IIC_CR_TX_FIFO_RESET_MASK 0x00000002
89#define IIC_CR_MSMS_MASK 0x00000004
90#define IIC_CR_DIR_IS_TX_MASK 0x00000008
91#define IIC_CR_NO_ACK_MASK 0x00000010
92#define IIC_CR_REPEATED_START_MASK 0x00000020
93#define IIC_CR_GENERAL_CALL_MASK 0x00000040
95#define IIC_INTR_ARB_LOST_MASK 0x00000001
96#define IIC_INTR_TX_ERROR_MASK 0x00000002
97#define IIC_INTR_TX_EMPTY_MASK 0x00000004
98#define IIC_INTR_RX_FULL_MASK 0x00000008
99#define IIC_INTR_BNB_MASK 0x00000010
100#define IIC_INTR_AAS_MASK 0x00000020
101#define IIC_INTR_NAAS_MASK 0x00000040
102#define IIC_INTR_TX_HALF_MASK 0x00000080
103#define IIC_SR_BUS_BUSY_MASK 0x00000004
104#define IIC_SR_RX_FIFO_EMPTY 0x00000040
105#define IIC_REG_SOFT_RESET (0x40)
106#define IIC_SR_MSTR_RDING_SLAVE_MASK 0x00000008
107
108void iic_init(const iic_index_t iic) {
109 if (!(iic >= IIC0 && iic < NUM_IICS)) {
110 pynq_error("invalid IIC %d, must be 0..%d\n", iic, NUM_IICS);
111 }
112 if (iic == IIC0) {
113 iic_handles[iic].ptr =
114 arm_shared_init(&((iic_handles[iic].mem_handle)), axi_iic_0, 4096);
115 } else if (iic == IIC1) {
116 iic_handles[iic].ptr =
117 arm_shared_init(&((iic_handles[iic].mem_handle)), axi_iic_1, 4096);
118 }
119 // Reset
120 (iic_handles[iic].ptr[IIC_REG_SOFT_RESET / 4]) = 0xA;
121 usleep(1000);
122}
123
124void iic_destroy(const iic_index_t iic) {
125 if (!(iic >= IIC0 && iic < NUM_IICS)) {
126 pynq_error("invalid IIC %d, must be 0..%d-1\n", iic, NUM_IICS);
127 }
128 if (iic_handles[iic].ptr == NULL) {
129 pynq_error("IIC%d has not been initialized.\n", iic);
130 }
131 arm_shared_close(&((iic_handles[iic].mem_handle)));
132 iic_handles[iic].ptr = NULL;
133}
134
135bool iic_set_slave_mode(const iic_index_t iic, const uint8_t addr,
136 uint32_t *register_map, const uint32_t rm_length) {
137 if (!(iic >= IIC0 && iic < NUM_IICS)) {
138 pynq_error("invalid IIC %d, must be 0..%d-1\n", iic, NUM_IICS);
139 }
140 if (iic_handles[iic].ptr == NULL) {
141 pynq_error("IIC%d has not been initialized.\n", iic);
142 }
143 (iic_handles[iic].saddr) = addr;
144 (iic_handles[iic].ptr[IIC_ADR_REG_OFFSET / 4]) = addr << 1;
145 uint32_t ctr_reg = (iic_handles[iic].ptr[IIC_CR_REG_OFFSET / 4]);
146 // Clear the master bit.
147 ctr_reg &= ~(IIC_CR_MSMS_MASK);
148 // Enable IIC
149 ctr_reg |= IIC_CR_ENABLE_DEVICE_MASK;
150
151 (iic_handles[iic].ptr[IIC_CR_REG_OFFSET / 4]) = ctr_reg;
152 (iic_handles[iic].ptr[IIC_RFD_REG_OFFSET / 4]) = 0x0;
153
154 iic_handles[iic].register_map = register_map;
155 iic_handles[iic].register_map_length = rm_length;
156
157 return true;
158}
159
160static inline void iic_clear_isr_mask(const iic_index_t iic, uint32_t mask) {
161
162 (iic_handles[iic].ptr[IIC_IISR_OFFSET / 4]) =
163 (iic_handles[iic].ptr[IIC_IISR_OFFSET / 4]) & mask;
164}
165
166static void iic_flush_tx_fifo(const iic_index_t iic) {
167 IICHandle *handle = &(iic_handles[iic]);
168 uint32_t reg = handle->ptr[IIC_CR_REG_OFFSET / 4];
170 handle->ptr[IIC_CR_REG_OFFSET / 4] = reg;
171}
172
173static void iic_tx_error_handler(const iic_index_t iic) {
174 IICHandle *handle = &(iic_handles[iic]);
175 iic_flush_tx_fifo(iic);
176 iic_clear_isr_mask(iic, IIC_INTR_RX_FULL_MASK | IIC_INTR_TX_HALF_MASK |
178
179 uint32_t reg = handle->ptr[IIC_CR_REG_OFFSET / 4];
180 handle->ptr[IIC_CR_REG_OFFSET / 4] = reg & ~IIC_CR_MSMS_MASK;
181}
182static void iic_slave_master_write(const iic_index_t iic, const uint32_t c) {
183 IICHandle *handle = &(iic_handles[iic]);
184 uint32_t v = (c << (handle->recv_cnt) * 8);
185 handle->new_val |= v;
186 handle->recv_cnt++;
187 // If we have one full word, write it back to register.
188 if (handle->recv_cnt == 4) {
189 handle->register_map[handle->selected_register %
190 handle->register_map_length] = handle->new_val;
191 // go to idle mode.
192 handle->state = IIC_IDLE;
193 }
194}
195
196static void iic_slave_master_read(const iic_index_t iic) {
197 IICHandle *handle = &(iic_handles[iic]);
198 if (handle->state == IIC_ADDRESS) {
199 handle->state = IIC_WRITE;
200 }
201 if (handle->state == IIC_WRITE) {
202 uint32_t r = (handle->register_map[handle->selected_register %
203 handle->register_map_length]);
204 uint8_t c = (r >> ((handle->recv_cnt) * 8)) & 0xFF;
205 (iic_handles[iic].ptr[IIC_DTR_REG_OFFSET / 4]) = c;
206 handle->recv_cnt++;
207 if (handle->recv_cnt == 4) {
208 // printf("1\n");
209 handle->state = IIC_IDLE;
210 }
211 // modulo 4;
212 handle->recv_cnt &= 0x03;
213 }
214};
215static void iic_interrupt_handle(const iic_index_t iic) {
216 time_t start = time(NULL);
217 IICHandle *handle = &(iic_handles[iic]);
218 int loop = 1;
219 uint32_t sr_reg = (handle->ptr[IIC_SR_REG_OFFSET / 4]);
220 do {
221 time_t now = time(NULL);
222 uint32_t nisr = (handle->ptr[IIC_IISR_OFFSET / 4]);
223 uint32_t clear = 0;
224 uint32_t isr = 0;
225 isr = nisr;
226 if (isr & IIC_INTR_ARB_LOST_MASK) {
227
229 } else if (isr & IIC_INTR_TX_ERROR_MASK) {
230 iic_tx_error_handler(iic);
231 handle->state = IIC_IDLE;
233 } else if (isr & IIC_INTR_RX_FULL_MASK) {
234 // if there is data in outgoing fifo, flush this.
235 uint8_t d = handle->ptr[IIC_DRR_REG_OFFSET / 4];
236
237 uint32_t reg = handle->ptr[IIC_CR_REG_OFFSET / 4];
238 reg &= ~IIC_CR_NO_ACK_MASK;
239 handle->ptr[IIC_CR_REG_OFFSET / 4] = reg;
240 switch (handle->state) {
241 case IIC_IDLE:
242 handle->recv_cnt = 0;
243 handle->new_val = 0;
244 handle->selected_register = d;
245 handle->state = IIC_ADDRESS;
246 break;
247 case IIC_ADDRESS:
248 handle->state = IIC_WRITE;
249 // FALLTHROUGH
250 case IIC_WRITE:
251 iic_slave_master_write(iic, d);
252 start = now;
253 break;
254 default:
255 pynq_warning("unhandled");
256 break;
257 }
258
259 clear = IIC_INTR_RX_FULL_MASK;
260 } else if (handle->addressed && (isr & IIC_INTR_NAAS_MASK)) {
261 handle->addressed = 0;
262
263 clear = IIC_INTR_NAAS_MASK;
264 } else if (!handle->addressed && (isr & IIC_INTR_AAS_MASK)) {
265 handle->addressed = 1;
266 clear = IIC_INTR_AAS_MASK;
267 } else if (isr & IIC_INTR_BNB_MASK) {
268 loop = 0;
269
270 clear = IIC_INTR_BNB_MASK;
271 } else if (isr & (IIC_INTR_TX_EMPTY_MASK | IIC_INTR_TX_HALF_MASK)) {
272
273 if (handle->state == IIC_ADDRESS || handle->state == IIC_WRITE) {
274 if (sr_reg & IIC_SR_MSTR_RDING_SLAVE_MASK) {
275 iic_slave_master_read(iic);
276 start = now;
277 }
278 }
280 }
281
282 if ((now - start) > IIC_TIMEOUT) {
283 pynq_warning("IIC timeout, resetting bus.");
284 iic_reset(iic);
285 iic_clear_isr_mask(iic, 0xFF);
286 uint32_t ctr_reg = (handle->ptr[IIC_CR_REG_OFFSET / 4]);
287 (iic_handles[iic].ptr[IIC_ADR_REG_OFFSET / 4]) = handle->saddr << 1;
288 // Clear the master bit.
289 ctr_reg &= ~(IIC_CR_MSMS_MASK);
290 // Enable IIC
291 ctr_reg |= IIC_CR_ENABLE_DEVICE_MASK;
292
293 (handle->ptr[IIC_CR_REG_OFFSET / 4]) = ctr_reg;
294 loop = 0;
295 }
296 //(iic_handles[iic].ptr[IIC_IISR_OFFSET / 4]) = nisr;
297 iic_clear_isr_mask(iic, clear);
298 sr_reg = (handle->ptr[IIC_SR_REG_OFFSET / 4]);
299 } while (loop && (sr_reg & IIC_SR_BUS_BUSY_MASK));
300 // iic_clear_isr_mask(iic, 0xFF);
301}
303
304 if (!(iic >= IIC0 && iic < NUM_IICS)) {
305 pynq_error("invalid IIC %d, must be 0..%d-1\n", iic, NUM_IICS);
306 }
307 if (iic_handles[iic].ptr == NULL) {
308 pynq_error("IIC%d has not been initialized.\n", iic);
309 }
310 iic_interrupt_handle(iic);
311 return;
312}
313
314void iic_reset(const iic_index_t iic) {
315 if (!(iic >= IIC0 && iic < NUM_IICS)) {
316 pynq_error("invalid IIC %d, must be 0..%d-1\n", iic, NUM_IICS);
317 }
318 if (iic_handles[iic].ptr == NULL) {
319 pynq_error("IIC%d has not been initialized.\n", iic);
320 }
321 iic_handles[iic].ptr[IIC_REG_SOFT_RESET / 4] = 0x0A;
322 uint32_t reg = iic_handles[iic].ptr[IIC_CR_REG_OFFSET / 4];
323 iic_handles[iic].ptr[IIC_CR_REG_OFFSET / 4] =
324 reg & ~IIC_CR_REPEATED_START_MASK;
325}
326
327bool iic_read_register(const iic_index_t iic, const uint8_t addr,
328 const uint8_t reg, uint8_t *data, uint16_t data_length) {
329 if (!(iic >= IIC0 && iic < NUM_IICS)) {
330 pynq_error("invalid IIC %d, must be 0..%d-1\n", iic, NUM_IICS);
331 }
332 if (iic_handles[iic].ptr == NULL) {
333 pynq_error("IIC%d has not been initialized.\n", iic);
334 }
335 if (XIic_Send((UINTPTR)iic_handles[iic].ptr, addr, (u8 *)&reg, 1,
336 XIIC_REPEATED_START) != 1) {
337 return 1;
338 }
339 uint8_t ByteCount = XIic_Recv((UINTPTR)iic_handles[iic].ptr, addr, data,
340 data_length, XIIC_STOP);
341 return (ByteCount == data_length) ? 0 : 1;
342}
343
344bool iic_write_register(const iic_index_t iic, const uint8_t addr,
345 const uint8_t reg, uint8_t *data,
346 uint16_t data_length) {
347 if (!(iic >= IIC0 && iic < NUM_IICS)) {
348 pynq_error("invalid IIC %d, must be 0..%d-1\n", iic, NUM_IICS);
349 }
350 if (iic_handles[iic].ptr == NULL) {
351 pynq_error("IIC%d has not been initialized.\n", iic);
352 }
353 uint8_t buffer[1 + data_length];
354 buffer[0] = reg;
355 memcpy(&(buffer[1]), data, data_length);
356 uint8_t ByteCount = XIic_Send((UINTPTR)iic_handles[iic].ptr, addr,
357 &(buffer[0]), 1 + data_length, XIIC_STOP);
358 return (ByteCount == (data_length + 1)) ? 0 : 1;
359}
void arm_shared_close(arm_shared *handle)
void * arm_shared_init(arm_shared *handle, const uint32_t address, const uint32_t length)
iic_index_t
Enum of IICs. Functions use a switch numbered from 0..NUM_IICS-1.
Definition iic.h:42
void iic_destroy(const iic_index_t iic)
Close the shared memory handle for the specified IIC index.
Definition iic.c:124
bool iic_set_slave_mode(const iic_index_t iic, const uint8_t addr, uint32_t *register_map, const uint32_t rm_length)
Definition iic.c:135
bool iic_write_register(const iic_index_t iic, const uint8_t addr, const uint8_t reg, uint8_t *data, uint16_t data_length)
Definition iic.c:344
bool iic_read_register(const iic_index_t iic, const uint8_t addr, const uint8_t reg, uint8_t *data, uint16_t data_length)
Definition iic.c:327
void iic_reset(const iic_index_t iic)
Definition iic.c:314
void iic_slave_mode_handler(const iic_index_t iic)
Definition iic.c:302
void iic_init(const iic_index_t iic)
Initialize the IIC specified by the index with a shared memory handle and a buffer size of 4096 bytes...
Definition iic.c:108
@ IIC1
Definition iic.h:42
@ IIC0
Definition iic.h:42
@ NUM_IICS
Definition iic.h:42
#define pynq_error(...)
Definition log.h:118
#define pynq_warning(...)
Definition log.h:109
#define IIC_INTR_TX_HALF_MASK
Definition iic.c:102
#define IIC_IISR_OFFSET
Definition iic.c:73
#define IIC_INTR_ARB_LOST_MASK
Definition iic.c:95
#define IIC_CR_TX_FIFO_RESET_MASK
Definition iic.c:88
#define IIC_CR_MSMS_MASK
Definition iic.c:89
#define IIC_DTR_REG_OFFSET
Definition iic.c:78
#define IIC_INTR_AAS_MASK
Definition iic.c:100
IICState
Definition iic.c:34
@ IIC_WRITE
Definition iic.c:38
@ IIC_ADDRESS
Definition iic.c:36
@ IIC_READ
Definition iic.c:37
@ IIC_IDLE
Definition iic.c:35
#define IIC_ADR_REG_OFFSET
Definition iic.c:80
#define IIC_SR_REG_OFFSET
Definition iic.c:77
#define IIC_INTR_TX_ERROR_MASK
Definition iic.c:96
#define IIC_SR_MSTR_RDING_SLAVE_MASK
Definition iic.c:106
#define IIC_DRR_REG_OFFSET
Definition iic.c:79
#define IIC_INTR_BNB_MASK
Definition iic.c:99
#define IIC_SR_BUS_BUSY_MASK
Definition iic.c:103
#define IIC_CR_REG_OFFSET
Definition iic.c:76
#define IIC_INTR_NAAS_MASK
Definition iic.c:101
#define IIC_RFD_REG_OFFSET
Definition iic.c:84
#define IIC_TIMEOUT
Definition iic.c:33
#define IIC_INTR_TX_EMPTY_MASK
Definition iic.c:97
#define IIC_CR_ENABLE_DEVICE_MASK
Definition iic.c:87
#define IIC_REG_SOFT_RESET
Definition iic.c:105
#define IIC_INTR_RX_FULL_MASK
Definition iic.c:98
int addressed
Definition iic.c:55
uint32_t * register_map
Definition iic.c:47
uint32_t selected_register
Definition iic.c:51
uint32_t recv_cnt
Definition iic.c:53
uint32_t register_map_length
Definition iic.c:48
arm_shared mem_handle
Definition iic.c:43
IICState state
Definition iic.c:54
uint8_t saddr
Definition iic.c:50
uint32_t new_val
Definition iic.c:52
volatile uint32_t * ptr
Definition iic.c:44
unsigned XIic_Recv(UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option)
Definition xiic_l.c:117
unsigned XIic_Send(UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option)
Definition xiic_l.c:373
#define XIIC_STOP
Definition xiic_l.h:216
#define XIIC_REPEATED_START
Definition xiic_l.h:219