libpynq (release 5EWC0-2023 version 0.2.1 of 2023-09-01 11:02)
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xiic_l.h
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1/******************************************************************************
2 * Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 ******************************************************************************/
5
6/****************************************************************************/
60#ifndef XIIC_L_H /* prevent circular inclusions */
61#define XIIC_L_H /* by using protection macros */
62
63#ifdef __cplusplus
64extern "C" {
65#endif
66
67/***************************** Include Files ********************************/
68
69#include "xil_io.h"
70#include "xil_types.h"
71
72/************************** Constant Definitions ****************************/
73
78#define XIIC_DGIER_OFFSET 0x1C
79#define XIIC_IISR_OFFSET 0x20
80#define XIIC_IIER_OFFSET 0x28
81#define XIIC_RESETR_OFFSET 0x40
82#define XIIC_CR_REG_OFFSET 0x100
83#define XIIC_SR_REG_OFFSET 0x104
84#define XIIC_DTR_REG_OFFSET 0x108
85#define XIIC_DRR_REG_OFFSET 0x10C
86#define XIIC_ADR_REG_OFFSET 0x110
87#define XIIC_TFO_REG_OFFSET 0x114
88#define XIIC_RFO_REG_OFFSET 0x118
89#define XIIC_TBA_REG_OFFSET 0x11C
90#define XIIC_RFD_REG_OFFSET 0x120
91#define XIIC_GPO_REG_OFFSET 0x124
92/* @} */
93
98#define XIIC_GINTR_ENABLE_MASK 0x80000000
99/* @} */
100
116#define XIIC_INTR_ARB_LOST_MASK 0x00000001
117#define XIIC_INTR_TX_ERROR_MASK 0x00000002
118#define XIIC_INTR_TX_EMPTY_MASK 0x00000004
119#define XIIC_INTR_RX_FULL_MASK 0x00000008
120#define XIIC_INTR_BNB_MASK 0x00000010
121#define XIIC_INTR_AAS_MASK 0x00000020
122#define XIIC_INTR_NAAS_MASK 0x00000040
123#define XIIC_INTR_TX_HALF_MASK 0x00000080
128#define XIIC_TX_INTERRUPTS \
129 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
130
134#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
135
136/* @} */
137
142#define XIIC_RESET_MASK 0x0000000A
143/* @} */
144
149#define XIIC_CR_ENABLE_DEVICE_MASK 0x00000001
150#define XIIC_CR_TX_FIFO_RESET_MASK 0x00000002
151#define XIIC_CR_MSMS_MASK 0x00000004
152#define XIIC_CR_DIR_IS_TX_MASK 0x00000008
153#define XIIC_CR_NO_ACK_MASK 0x00000010
154#define XIIC_CR_REPEATED_START_MASK 0x00000020
155#define XIIC_CR_GENERAL_CALL_MASK 0x00000040
156/* @} */
157
162#define XIIC_SR_GEN_CALL_MASK \
163 0x00000001
165#define XIIC_SR_ADDR_AS_SLAVE_MASK \
166 0x00000002
168#define XIIC_SR_BUS_BUSY_MASK 0x00000004
169#define XIIC_SR_MSTR_RDING_SLAVE_MASK \
170 0x00000008
172#define XIIC_SR_TX_FIFO_FULL_MASK 0x00000010
173#define XIIC_SR_RX_FIFO_FULL_MASK 0x00000020
174#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x00000040
175#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x00000080
176/* @} */
177
182#define XIIC_TX_DYN_START_MASK 0x00000100
183#define XIIC_TX_DYN_STOP_MASK 0x00000200
184#define IIC_TX_FIFO_DEPTH 16
185/* @} */
186
191#define IIC_RX_FIFO_DEPTH 16
192/* @} */
193
194#define XIIC_TX_ADDR_SENT 0x00
195#define XIIC_TX_ADDR_MSTR_RECV_MASK 0x02
196
201#define XIIC_READ_OPERATION 1
202#define XIIC_WRITE_OPERATION 0
208#define XIIC_MASTER_ROLE 1
209#define XIIC_SLAVE_ROLE 0
216#define XIIC_STOP \
217 0x00
219#define XIIC_REPEATED_START \
220 0x01
223/***************** Macros (Inline Functions) Definitions *********************/
224
225#define XIic_In32 Xil_In32
226#define XIic_Out32 Xil_Out32
227
228/****************************************************************************/
247#define XIic_ReadReg(BaseAddress, RegOffset) \
248 XIic_In32((BaseAddress) + (RegOffset))
249
250/***************************************************************************/
270#define XIic_WriteReg(BaseAddress, RegOffset, RegisterValue) \
271 XIic_Out32((BaseAddress) + (RegOffset), (RegisterValue))
272
273/******************************************************************************/
287#define XIic_IntrGlobalDisable(BaseAddress) \
288 XIic_WriteReg((BaseAddress), XIIC_DGIER_OFFSET, 0)
289
290/******************************************************************************/
305#define XIic_IntrGlobalEnable(BaseAddress) \
306 XIic_WriteReg((BaseAddress), XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK)
307
308/******************************************************************************/
324#define XIic_IsIntrGlobalEnabled(BaseAddress) \
325 (XIic_ReadReg((BaseAddress), XIIC_DGIER_OFFSET) == XIIC_GINTR_ENABLE_MASK)
326
327/******************************************************************************/
352#define XIic_WriteIisr(BaseAddress, Status) \
353 XIic_WriteReg((BaseAddress), XIIC_IISR_OFFSET, (Status))
354
355/******************************************************************************/
371#define XIic_ReadIisr(BaseAddress) XIic_ReadReg((BaseAddress), XIIC_IISR_OFFSET)
372
373/******************************************************************************/
394#define XIic_WriteIier(BaseAddress, Enable) \
395 XIic_WriteReg((BaseAddress), XIIC_IIER_OFFSET, (Enable))
396
397/******************************************************************************/
414#define XIic_ReadIier(BaseAddress) XIic_ReadReg((BaseAddress), XIIC_IIER_OFFSET)
415
416/******************************************************************************/
432#define XIic_ClearIisr(BaseAddress, InterruptMask) \
433 XIic_WriteIisr((BaseAddress), XIic_ReadIisr(BaseAddress) & (InterruptMask))
434
435/******************************************************************************/
453#define XIic_Send7BitAddress(BaseAddress, SlaveAddress, Operation) \
454 { \
455 u8 LocalAddr = (u8)(SlaveAddress << 1); \
456 LocalAddr = (LocalAddr & 0xFE) | (Operation); \
457 XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET, LocalAddr); \
458 }
459
460/******************************************************************************/
479#define XIic_DynSend7BitAddress(BaseAddress, SlaveAddress, Operation) \
480 { \
481 u8 LocalAddr = (u8)(SlaveAddress << 1); \
482 LocalAddr = (LocalAddr & 0xFE) | (Operation); \
483 XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET, \
484 XIIC_TX_DYN_START_MASK | LocalAddr); \
485 }
486
487/******************************************************************************/
506#define XIic_DynSendStartStopAddress(BaseAddress, SlaveAddress, Operation) \
507 { \
508 u8 LocalAddr = (u8)(SlaveAddress << 1); \
509 LocalAddr = (LocalAddr & 0xFE) | (Operation); \
510 XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET, \
511 XIIC_TX_DYN_START_MASK | XIIC_TX_DYN_STOP_MASK | LocalAddr); \
512 }
513
514/******************************************************************************/
529#define XIic_DynSendStop(BaseAddress, ByteCount) \
530 { \
531 XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET, \
532 XIIC_TX_DYN_STOP_MASK | ByteCount); \
533 }
534
535/************************** Function Prototypes *****************************/
536
537unsigned XIic_Recv(UINTPTR BaseAddress, u8 Address, u8 *BufferPtr,
538 unsigned ByteCount, u8 Option);
539
540unsigned XIic_Send(UINTPTR BaseAddress, u8 Address, u8 *BufferPtr,
541 unsigned ByteCount, u8 Option);
542
543unsigned XIic_DynRecv(UINTPTR BaseAddress, u8 Address, u8 *BufferPtr,
544 u8 ByteCount);
545
546unsigned XIic_DynSend(UINTPTR BaseAddress, u16 Address, u8 *BufferPtr,
547 u8 ByteCount, u8 Option);
548
549int XIic_DynInit(UINTPTR BaseAddress);
550
551u32 XIic_CheckIsBusBusy(UINTPTR BaseAddress);
552
553u32 XIic_WaitBusFree(UINTPTR BaseAddress);
554
555#ifdef __cplusplus
556}
557#endif
558
559#endif /* end of protection macro */
int XIic_DynInit(UINTPTR BaseAddress)
Definition xiic_l.c:10
u32 XIic_CheckIsBusBusy(UINTPTR BaseAddress)
Definition xiic_l.c:11
unsigned XIic_Recv(UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option)
Definition xiic_l.c:2
unsigned XIic_Send(UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option)
Definition xiic_l.c:4
u32 XIic_WaitBusFree(UINTPTR BaseAddress)
Definition xiic_l.c:12
unsigned XIic_DynRecv(UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, u8 ByteCount)
Definition xiic_l.c:6
unsigned XIic_DynSend(UINTPTR BaseAddress, u16 Address, u8 *BufferPtr, u8 ByteCount, u8 Option)
Definition xiic_l.c:8