libpynq (release 5EWC0-2023 version 0.2.1 of 2023-09-01 11:02)
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xiic_i.h
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1/******************************************************************************
2 * Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 ******************************************************************************/
5
6/*****************************************************************************/
50#ifndef XIIC_I_H /* prevent circular inclusions */
51#define XIIC_I_H /* by using protection macros */
52
53#ifdef __cplusplus
54extern "C" {
55#endif
56
57/***************************** Include Files *********************************/
58
59#include "xiic.h"
60#include "xil_assert.h"
61#include "xil_types.h"
62#include "xstatus.h"
63
64/************************** Constant Definitions *****************************/
65
66/**************************** Type Definitions *******************************/
67
68/***************** Macros (Inline Functions) Definitions *********************/
69
70/******************************************************************************
71 *
72 * This macro sends the first byte of the address for a 10 bit address during
73 * both read and write operations. It takes care of the details to format the
74 * address correctly.
75 *
76 * address = 1111_0xxD xx = address MSBits
77 * D = Tx direction = 0 = write
78 *
79 * @param SlaveAddress contains the address of the slave to send to.
80 * @param Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION
81 *
82 * @return None.
83 *
84 * @note Signature:
85 * void XIic_Send10BitAddrByte1(u16 SlaveAddress, u8 Operation);
86 *
87 ******************************************************************************/
88#define XIic_Send10BitAddrByte1(SlaveAddress, Operation) \
89 { \
90 u8 LocalAddr = (u8)((SlaveAddress) >> 7); \
91 LocalAddr = (LocalAddr & 0xF6) | 0xF0 | (Operation); \
92 XIic_WriteReg(InstancePtr->BaseAddress, XIIC_DTR_REG_OFFSET, \
93 (u32)LocalAddr); \
94 }
95
96/******************************************************************************
97 *
98 * This macro sends the second byte of the address for a 10 bit address during
99 * both read and write operations. It takes care of the details to format the
100 * address correctly.
101 *
102 * @param SlaveAddress contains the address of the slave to send to.
103 *
104 * @return None.
105 *
106 * @note Signature: void XIic_Send10BitAddrByte2(u16
107 *SlaveAddress, u8 Operation);
108 *
109 ******************************************************************************/
110#define XIic_Send10BitAddrByte2(SlaveAddress) \
111 XIic_WriteReg(InstancePtr->BaseAddress, XIIC_DTR_REG_OFFSET, \
112 (u32)(SlaveAddress));
113
114/******************************************************************************
115 *
116 * This macro sends the address for a 7 bit address during both read and write
117 * operations. It takes care of the details to format the address correctly.
118 *
119 * @param SlaveAddress contains the address of the slave to send to.
120 * @param Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION
121 *
122 * @return None.
123 *
124 * @note Signature:
125 * void XIic_Send7BitAddr(u16 SlaveAddress, u8 Operation);
126 *
127 ******************************************************************************/
128#define XIic_Send7BitAddr(SlaveAddress, Operation) \
129 { \
130 u8 LocalAddr = (u8)(SlaveAddress << 1); \
131 LocalAddr = (LocalAddr & 0xFE) | (Operation); \
132 XIic_WriteReg(InstancePtr->BaseAddress, XIIC_DTR_REG_OFFSET, \
133 (u32)LocalAddr); \
134 }
135
136/******************************************************************************
137 *
138 * This macro disables the specified interrupts in the Interrupt enable
139 * register. It is non-destructive in that the register is read and only the
140 * interrupts specified is changed.
141 *
142 * @param BaseAddress is the base address of the IIC device.
143 * @param InterruptMask contains the interrupts to be disabled
144 *
145 * @return None.
146 *
147 * @note Signature:
148 * void XIic_DisableIntr(u32 BaseAddress, u32 InterruptMask);
149 *
150 ******************************************************************************/
151#define XIic_DisableIntr(BaseAddress, InterruptMask) \
152 XIic_WriteIier((BaseAddress), XIic_ReadIier(BaseAddress) & ~(InterruptMask))
153
154/******************************************************************************
155 *
156 * This macro enables the specified interrupts in the Interrupt enable
157 * register. It is non-destructive in that the register is read and only the
158 * interrupts specified is changed.
159 *
160 * @param BaseAddress is the base address of the IIC device.
161 * @param InterruptMask contains the interrupts to be disabled
162 *
163 * @return None.
164 *
165 * @note Signature:
166 * void XIic_EnableIntr(u32 BaseAddress, u32 InterruptMask);
167 *
168 ******************************************************************************/
169#define XIic_EnableIntr(BaseAddress, InterruptMask) \
170 XIic_WriteIier((BaseAddress), XIic_ReadIier(BaseAddress) | (InterruptMask))
171
172/******************************************************************************
173 *
174 * This macro clears the specified interrupt in the Interrupt status
175 * register. It is non-destructive in that the register is read and only the
176 * interrupt specified is cleared. Clearing an interrupt acknowledges it.
177 *
178 * @param BaseAddress is the base address of the IIC device.
179 * @param InterruptMask contains the interrupts to be disabled
180 *
181 * @return None.
182 *
183 * @note Signature:
184 * void XIic_ClearIntr(u32 BaseAddress, u32 InterruptMask);
185 *
186 ******************************************************************************/
187#define XIic_ClearIntr(BaseAddress, InterruptMask) \
188 XIic_WriteIisr((BaseAddress), XIic_ReadIisr(BaseAddress) & (InterruptMask))
189
190/******************************************************************************
191 *
192 * This macro clears and enables the specified interrupt in the Interrupt
193 * status and enable registers. It is non-destructive in that the registers are
194 * read and only the interrupt specified is modified.
195 * Clearing an interrupt acknowledges it.
196 *
197 * @param BaseAddress is the base address of the IIC device.
198 * @param InterruptMask contains the interrupts to be cleared and enabled
199 *
200 * @return None.
201 *
202 * @note Signature:
203 * void XIic_ClearEnableIntr(u32 BaseAddress, u32 InterruptMask);
204 *
205 ******************************************************************************/
206#define XIic_ClearEnableIntr(BaseAddress, InterruptMask) \
207 { \
208 XIic_WriteIisr(BaseAddress, \
209 (XIic_ReadIisr(BaseAddress) & (InterruptMask))); \
210 \
211 XIic_WriteIier(BaseAddress, \
212 (XIic_ReadIier(BaseAddress) | (InterruptMask))); \
213 }
214
215/******************************************************************************
216 *
217 * This macro flushes the receive FIFO such that all bytes contained within it
218 * are discarded.
219 *
220 * @param InstancePtr is a pointer to the IIC instance containing the FIFO
221 * to be flushed.
222 *
223 * @return None.
224 *
225 * @note Signature:
226 * void XIic_FlushRxFifo(XIic *InstancePtr);
227 *
228 ******************************************************************************/
229#define XIic_FlushRxFifo(InstancePtr) \
230 { \
231 int LoopCnt; \
232 u8 BytesToRead = \
233 XIic_ReadReg(InstancePtr->BaseAddress, XIIC_RFO_REG_OFFSET) + 1; \
234 for (LoopCnt = 0; LoopCnt < BytesToRead; LoopCnt++) { \
235 XIic_ReadReg(InstancePtr->BaseAddress, XIIC_DRR_REG_OFFSET); \
236 } \
237 }
238
239/******************************************************************************
240 *
241 * This macro flushes the transmit FIFO such that all bytes contained within it
242 * are discarded.
243 *
244 * @param InstancePtr is a pointer to the IIC instance containing the FIFO
245 * to be flushed.
246 *
247 * @return None.
248 *
249 * @note Signature:
250 * void XIic_FlushTxFifo(XIic *InstancePtr);
251 *
252 ******************************************************************************/
253#define XIic_FlushTxFifo(InstancePtr) \
254 ; \
255 { \
256 u32 CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET); \
257 XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET, \
258 CntlReg | XIIC_CR_TX_FIFO_RESET_MASK); \
259 XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET, CntlReg); \
260 }
261
262/******************************************************************************
263 *
264 * This macro reads the next available received byte from the receive FIFO
265 * and updates all the data structures to reflect it.
266 *
267 * @param InstancePtr is a pointer to the IIC instance to be operated on.
268 *
269 * @return None.
270 *
271 * @note Signature:
272 * void XIic_ReadRecvByte(XIic *InstancePtr);
273 *
274 ******************************************************************************/
275#define XIic_ReadRecvByte(InstancePtr) \
276 { \
277 *InstancePtr->RecvBufferPtr++ = \
278 XIic_ReadReg(InstancePtr->BaseAddress, XIIC_DRR_REG_OFFSET); \
279 InstancePtr->RecvByteCount--; \
280 InstancePtr->Stats.RecvBytes++; \
281 }
282
283/******************************************************************************
284 *
285 * This macro writes the next byte to be sent to the transmit FIFO
286 * and updates all the data structures to reflect it.
287 *
288 * @param InstancePtr is a pointer to the IIC instance to be operated on.
289 *
290 * @return None.
291 *
292 * @note Signature:
293 * void XIic_WriteSendByte(XIic *InstancePtr);
294 *
295 ******************************************************************************/
296#define XIic_WriteSendByte(InstancePtr) \
297 { \
298 XIic_WriteReg(InstancePtr->BaseAddress, XIIC_DTR_REG_OFFSET, \
299 *InstancePtr->SendBufferPtr++); \
300 InstancePtr->SendByteCount--; \
301 InstancePtr->Stats.SendBytes++; \
302 }
303
304/******************************************************************************
305 *
306 * This macro sets up the control register for a master receive operation.
307 * A write is necessary if a 10 bit operation is being performed.
308 *
309 * @param InstancePtr is a pointer to the IIC instance to be operated on.
310 * @param ControlRegister contains the contents of the IIC device control
311 * register
312 * @param ByteCount contains the number of bytes to be received for the
313 * master receive operation
314 *
315 * @return None.
316 *
317 * @note Signature:
318 * void XIic_SetControlRegister(XIic *InstancePtr,
319 * u8 ControlRegister,
320 * int ByteCount);
321 *
322 ******************************************************************************/
323#define XIic_SetControlRegister(InstancePtr, ControlRegister, ByteCount) \
324 { \
325 (ControlRegister) &= ~(XIIC_CR_NO_ACK_MASK | XIIC_CR_DIR_IS_TX_MASK); \
326 if (InstancePtr->Options & XII_SEND_10_BIT_OPTION) { \
327 (ControlRegister) |= XIIC_CR_DIR_IS_TX_MASK; \
328 } else { \
329 if ((ByteCount) == 1) { \
330 (ControlRegister) |= XIIC_CR_NO_ACK_MASK; \
331 } \
332 } \
333 }
334
335/************************** Function Prototypes ******************************/
336
337extern XIic_Config XIic_ConfigTable[];
338
339/* The following variables are shared across files of the driver and
340 * are function pointers that are necessary to break dependencies allowing
341 * optional parts of the driver to be used without condition compilation
342 */
343extern void (*XIic_AddrAsSlaveFuncPtr)(XIic *InstancePtr);
344extern void (*XIic_NotAddrAsSlaveFuncPtr)(XIic *InstancePtr);
345extern void (*XIic_RecvSlaveFuncPtr)(XIic *InstancePtr);
346extern void (*XIic_SendSlaveFuncPtr)(XIic *InstancePtr);
347extern void (*XIic_RecvMasterFuncPtr)(XIic *InstancePtr);
348extern void (*XIic_SendMasterFuncPtr)(XIic *InstancePtr);
349extern void (*XIic_ArbLostFuncPtr)(XIic *InstancePtr);
350extern void (*XIic_BusNotBusyFuncPtr)(XIic *InstancePtr);
351
352void XIic_TransmitFifoFill(XIic *InstancePtr, int Role);
353
354#ifdef __cplusplus
355}
356#endif
357
358#endif /* end of protection macro */
void(* XIic_ArbLostFuncPtr)(XIic *InstancePtr)
XIic_Config XIic_ConfigTable[]
void(* XIic_RecvMasterFuncPtr)(XIic *InstancePtr)
void(* XIic_NotAddrAsSlaveFuncPtr)(XIic *InstancePtr)
void(* XIic_SendSlaveFuncPtr)(XIic *InstancePtr)
void(* XIic_SendMasterFuncPtr)(XIic *InstancePtr)
void XIic_TransmitFifoFill(XIic *InstancePtr, int Role)
void(* XIic_BusNotBusyFuncPtr)(XIic *InstancePtr)
void(* XIic_AddrAsSlaveFuncPtr)(XIic *InstancePtr)
void(* XIic_RecvSlaveFuncPtr)(XIic *InstancePtr)